Gutting chip-testing costs: Designing VLSI circuits for testability is the most efficient way to reduce the relative costs of assuring high chip reliability
Sharad C. Seth, Vishwani D. Agrawal · IEEE Spectrum · 1985
Testing now accounts for 10% of the total cost of manufacturing a 1-kb random-access-memory chip. For a 64K RAM chip, the figure rises to 40%. New techniques, however, promise to hold down costs by tackling the circuit-testing problem in the design stage. The new methods include computer programs that assess during design how easily a circuit can be tested, scan-design techniques for testing sequential circuitry, and ways of partitioning chips into blocks of manageable size for testing. Random testing and built-in self-testing are also employed in some cases to avoid exhaustive testing for every possible fault in a circuit. These new methods are described.