Development of a VLSI chip set for H.261/MPEG-1 video codec
Eishi Morimatsu, Osamu Kawai, Kiyoshi Sakai, Kiichi Matsuda, H. Miyasaka, Hirokazu Fukui, Yasuhiro Sakawaki, Kazuo Kaneko, Katsuhiro Eguchi · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1993
A VLSI chip set fully compatible with both CCITT/H.261 and ISO/MPEG-1 has been developed. The chip set is composed of 3 chips, MC-LSI, COD-LSI, and DEC-LSI which realize a realtime coding of moving pictures based on the international standard coding algorithms. A realtime decoder can also be realized by single use of a DEC-LSI chip. Each chip includes 140,000 to 160,000 gates using 0.8 micrometers CMOS technology and operates at 27 MHz clock rate. The chip set performs full frame coding/decoding of CIF and SIF, and operates up to 6.3 Mb/s in the transmission bitrate. The chip set has been installed into a prototype video codec controlled by a PC(FM-TOWNS) and confirmed to work successfully.