Fault diagnosis in combinational digital circuits using a backtrack algorithm to generate fault location hypotheses
Stephen J. Sangwine · IEE Proceedings G (Electronic Circuits and Systems) · 1988
A backtrack algorithm for the generation of fault location hypotheses in combinational digital circuits is presented. The algorithm uses the results of applied tests and works back from incorrect circuit outputs to generate a list of possible single and/or multiple faults. Suggestions are given for refining the list by selecting probing measurements and by computing the intersection of more than one list resulting from multiple tests.