Design of high speed 32-bit parallel prefix adder for CMOS technology
S. Deo · China-Ireland International Conference on Information and Communications Technologies (CIICT 2007) · 2007
This paper describes the design requirement specification of a High-speed 32-bit parallel-prefix Adder. The parallel-prefix adder utilizes a parallel-prefix topology to reduce the critical path in the adder. The critical path is the carry generation path, has a logarithmic dependence of the bit-width, which should be compared to the linear dependence in the ripple carry adder. The author used Kogge-Stone Adder because it has one of the shortest critical paths of all other adders. A set of tools for architectural level synthesis of parallel adders is developed, which were module generator and a library of parameterized VHDL models. Reasonable levels of power consumption were investigated and for a 9.29 mW power simulation results, the total delay 2.829 ns in Kogge-stone Adder and maximum combinational path delay 8.586 ns.