Prototype Debug using ATE
David Florcik, David Low, Martin Roche · IEEE Design & Test of Computers · 1984
A less costly, less time-consuming method of design verification of printed circuit boards would permit a faster time-to-market in `today's highly competitive marketplace. Digital Equipment's staff devised a procedure that accelerates the process with ATE (using dynamic high-speed functional testing and a simulation pattern capturing process). This process also permits more rapid, more efficient, and more accurate fault isolation. For this method, the designer creates a hierarchical simulation scheme and writes design verfication tests. These tests are used to develop a test program for a prototype board. Interface signals for the next lower level of simulation must be modeled. The final simulation model must have all device-level interconnects modeled. (The level of automation determines the time required to produce a board test program.) This process emulates the final environment in which the board will be located and accomplishes a significant savings in time and cost.