A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability
Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara · 2001
This paper proposes a non-scan design-for-test-ability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.