Region-based caching
Hsien-Hsin S. Lee, Gary Tyson · 2000
Power consumption has been a major concern in designing microprocessors for portable systems such as notebook computers, hand-held computing and personal telecommunication devices.As these devices increase in popularity and are used in a wider range of applications, a low p o wer design becomes more critical.In this paper, we propose a new microarchitectural data cache design called region-based c aching that can reduce power consumption.Power savings is achieved by re-organizing the the rst level cache to more eÆciently exploit memory reference characteristics produced by programming language semantics.These characteristics enable the cache to be partitioned by memory region (stack, global, heap), reducing power consumption, while retaining comparable performance to a conventional cache design.Applications from the MediaBench b e n c hmark suite indicate that a design with two additional small region-based caches results in 66% reduction in average in energy-delay product.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific