A Binary-Tree Hierarchical Multiple-Chip Architecture for Real-Time Large-Scale Learning Processor Systems
Yitao Ma, Tadashi Shibata · Japanese Journal of Applied Physics · 2010
A binary-tree hierarchical multiple-chip processor architecture leveraging the K-means clustering algorithm has been developed for real-time learning of large amounts of sample data. To improve the computational speed, an embedded memory configuration has been used to store all sample data on the same chip for massively parallel processing. As a solution to the problem of the maximum sample data size limited by the chip area, a multiple-chip architecture has been developed, in which dedicated processor chips are connected in a binary-tree hierarchical structure. As a result, the system has been made extendible to any larger scale depending on the application needs. Furthermore, the pipeline calculation flow has been introduced to compensate for the interchip data communication delay. A proof-of-concept chip was designed using a 0.18 µm five-metal complementary metal–oxide–semiconductor (CMOS) technology. The chip operation was verified by NanoSim simulation, and pipeline calculation flow was demonstrated by test chip measurement.