Realisation of high-speed systolic IIR decimators and interpolators
Hon Keung Kwan · Electronics Letters · 1993
Two novel systolic allpass digital filtering arrays for realising high-speed systolic IIR decimators and interpolators are described. The sampling period at the input of such a decimator by N and at the output of such an interpolator by N can be reduced to (Tm+2Ta)/(N−1) and (Tm+3Ta)/N, respectively, by the two arrays. (Tm and Tn respectively, represent the times for twoinput real multiplication and two-input real addition.) Other advantages include reduced latencies, and reduced numbers of multipliers and adders.