The 3.0GHz 64-thread SPARC T4 processor
Jinuk Luke Shin, Robert Golia, Hongping Li, Sudesna Dash, Mary Jo Doherty, Greg Grohoski, Curtis McAllister · 2012
The SPARC T4 processor introduces the next generation multi-threaded S3 core and delivers a significant single-thread performance improvement over its predecessor. The chip integrates eight S3 cores, an 8-Bank 4MB L3 Cache, a 768GB/sec crossbar, a memory controller, PCI Gen2.0, 10G Ethernet and a cache coherency controller with 2.4Tb/s highspeed I/Os. The dual-issue, out-of-order execution core features a 16-stage integer pipeline, extensive branch predictions, dynamic threading and an enhanced cryptographic processing unit. The 406mm2die is fabricated in TSMC's 40nm process and contains 855million transistors and 2.6million flip-flops in a flipchip ceramic package. Enhanced physical design methodologies and extensive power management features enable 3.0GHz operation in the same power envelope of its predecessor.