Using combinational logic function to watermark IP based on FPGA
Mao Sheng, Dai Guanzhong, Dejun Mu, Meifeng Li · Wuhan University Journal of Natural Sciences · 2006
In the field of digital circuit design, the extensive applications of reusable intellectual property (IP) simplify the design procedure based on very large scale field programmable gate array (FPGA), and shorten the time to market (TTM). However, the flexibility of reusable IP makes itself easy to be stolen and illegally distributed by intruders. The protection method proposed in this aper maps IP owner's signature to combinational logic functions, and then implements these functions into unused lookup tables (LUTs) in the design based on FPGA, which can be used as a strong proof of IPs ownership. The related experiment results show that this protection method has favorable characteristics such as low overhead, few effects on performance, and high security.