Massively parallel architecture for quadratic digital filters
Dimitrios Hatzinakos, Chrysostomos L. Nikias, A.N. Venetsanopoulos · IEEE Transactions on Circuits and Systems · 1990
A massively parallel architecture for quadratic digital filters is introduced. It is obtained by using matrix and vector decomposition forms and consists of a set of parallel one-dimensional IIR (infinite-impulse-response) filters in cascade with square-in add-out types of operations. This architecture exhibits great modularity and regularity as well as flexibility and generality. The data throughput delay, cost (which is proportional to chip area), and roundoff error effects of the proposed structure are derived, and comparisons with other already available implementations are made.>