A 775-µW/fps/view H.264/MVC decoder chip compliant with 3D Blu-ray specifications
Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih‐Ming Wang, Chun-Chia Chen, Hue-Min Lin, Chia-Yun Cheng, Min-Hao Chiu, Sheng-Jen Wang, Ping Yi Chao, MJ Hu, Hao-Wei Li, Chung-Hung Tsai · 2012
A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a single die. Moreover, it features pipeline management and clock management units so as to improve the processing throughput and clock power efficiency. A test chip for not only single-view video but multi-view H.264/MVC decoding has been designed and fabricated using 40nm 1P7M CMOS process with core area 1.22mm2. Core power dissipation is about 46.5mW under 1920×1080 resolution of single view 60fps or stereo-view 30fps.