Area-efficient VLSI architecture for the tracebackViterbidecoder supporting punctured codes
Sik Kim, Sun-Young Hwang · Electronics Letters · 1996
The authors present a novel architecture designed to reduce the storage for decision vectors at the traceback block in the Viterbi decoder. By decreasing the rate of decision vector generation, the data storage requirement has been reduced by 29.9% in the proposed architecture compared to conventional traceback Viterbi decoders. The overall area has been reduced by ~25% when implemented in VLSI.