A method of hazard detection by five‐valued logic simulation based on the TRF delay model
Min Sup Kang, Hiroshi Deguchi, Isao Shirakawa · Electronics and Communications in Japan (Part III Fundamental Electronic Science) · 1992
Abstract This paper proposes an efficient method to detect the hazard existing in the logic circuit using the five‐valued logic simulator. The proposed method is effective in logic verification for the combinational and asynchronous and sequential logic circuits as well as the verification for the hazard (race). Using the proposed method, the timing of the logic circuit is analyzed, including the rise/fall delay considering the signal transition time. The hazard is detected based on the output of the gate and the scheduled time. Also discussion is a method of event cancellation, which is a problem in the delayed simulation. Through the results of experiments using several circuits, the proposed algorithm is shown to be useful.