4.3 Fine-grained adaptive power management of the SPARC M7 processor
Venkat Raghavan Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan Yanggong, Haowei Zhang · 2015
The power management system described in this paper enables more than 3× increase in power-constrained performance over the previous generation of SPARC server CPUs [2]. The low latency and high performance of the system is possible due to accurate, high-bandwidth sensors, fast on-die control and finegrained actuation implemented using both clock cycle skipping and DVFS, as required by the time constants of system constraints.