An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories
Xueqiang Wang, Dong Wu, Liyang Pan, Zhou Runde, Chaohong Hu · 2009
An on-chip high-speed 4-bit BCH decoder for error correcting in a MLC NOR flash memory is presented. As process shrinking beyond 45nm, double-error-correcting (DEC) BCH code is needed for reliability requirement. A novel fast-decoding algorithm is developed by eliminating finite field divisions and combining arithmetic operations. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of the 4-bit BCH decoder in a 2b/cell NOR flash memory is proposed to obtain a good time-area trade-off. Simulation results show that the latency of the 4-bit BCH decoder achieves only 6.4ns and satisfies fast access time of a NOR Flash memory.