The SARC Architecture
Alex Ramírez, Felipe Cabarcas, Ben Juurlink, Mauricio Álvarez-Mesa, Friman Sánchez, Arnaldo Azevedo, Cor Meenderinck, Cătălin Bogdan Ciobanu, Sebastián Isaza, Georgi Gaydadjiev · IEEE Micro · 2010
The SARC architecture is composed of multiple processor types and a set of user-managed direct memory access (DMA) engines that let the runtime scheduler overlap data transfer and computation. The runtime system automatically allocates tasks on the heterogeneous cores and schedules the data transfers through the DMA engines. SARC's programming model supports various highly parallel applications, with matching support from specialized accelerator processors.