An Energy-Efficient Processor Core for Massively Parallel Computing
Qianming Yang, Nan Wu, Maolin Guan, Chunyuan Zhang, Jun Cai · 2012
With the evolution of more sophisticated communication standards and algorithms, embedded applications exhibit demanding performance and efficiency requirements. Massively Parallel Computing based on many simple cores and few powerful cores is becoming the mainstream method of building high performance and low power processor. While aimed at the design of the simple core, this paper proposes an energy-efficient processor architecture named Smart Core. Following the idea of explicitly parallel and accurate computing, Smart Core uses exposed and non-deep pipeline to eliminate the pipeline registers and to reduce the cost of executing instructions. Multi-level data memory organization, consisted of streaming memory, multi-mode register file and fully distributed tiny operand register file, captures various data reuse and locality to reduce the cost of delivering data. To reduce the cost of delivering instructions, an asymmetric and fully distributed instruction register file is used to capture locality and reuse of instructions in a loop. Preliminary results show that Smart Core achieves an energy efficiency that is 25x greater than the traditional embedded RISC processor. When scaled to a 40nm CMOS technology, single chip multi-processor, consisted of many cores like Smart Core, is capable of providing more than 1TOPS performance while achieving efficiency of 100GOPS/W or more.