A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory
Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Ricky Kuo, Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Saysamone Pittikoun, R. Shirota, Chin-chen Cho · Proceedings of the International Power Modulator Symposium and High Voltage Workshop/Proceedings of the ... International Power Modulator Symposium and ... High Voltage Workshop · 2008
In this paper, we present our study of a method to improve nonuniform erasing speeds caused by slow edge cells (cell 0 and cell 31). Simulation and measurement results showed that the slow erasing speed at edge cells is resulted from the coupling effect of select gate (SG) transistors. Moreover, several extra bias voltages were forced on the pass wordlines to evaluate the electrostatic potential difference and to improve erase uniformity. Simulation result and measurement data demonstrated that 0.4 V of the extra bias voltage can improve the uniformity of the erasing speed in nano-scale NAND flash memory.