A 1-GHz direct digital frequency synthesizer in an FPGA
Matthew Ryan Bergeron, Alan N. Willson · 2014
The architecture and design of a high-speed quadrature direct digital frequency synthesizer (DDFS), implemented in an FPGA, is presented. The architecture is based on a novel multiplier-based angle-rotation algorithm that does not distort the magnitude of the sine and cosine outputs. This algorithm maps well into the DSP slices present in modern FPGAs. Implemented in a Xilinx Virtex-7 device, the design dissipates 54.9 mW of power at 1 GHz, a performance previously attainable only in ASIC designs.