Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs
Alexandre M. Amory, Cristiano Lazzari, Marcelo Soares Lubaszewski, Fernando Gehm Moraes · 2011
The use of existing Networks-on-Chip (NoCs) for test data transportation has been proposed to avoid conventional dedicated Test Access Mechanism (TAM), improving the modularity of the test architecture. This paper presents a wire length estimation method used to evaluate the cost of dedicated TAMs for NoC-based SoCs early in the design flow. This wire length information (together with test time, power dissipation, among other test metrics) can help the designer to decide the best test architecture (NoC TAM or dedicated TAM) for a given chip. The experimental results demonstrate that dedicated TAMs require, on average, 26% of the global wires, enforcing quantitatively the benefits of NoC TAMs. On the other hand, results can vary depending on the SoC, from 3% to 70%, demonstrating the need of a fast wire length estimation in early stages of design.