Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors
Nikolaos Bellas Ibrahim Hajj, George I. Stamoulis, Nikolaos Bellas, Constantine D. Polychronopoulos · 1998
In this paper we propose a technique that uses an additional mini cache located between the I-Cache and the CPU core, and buffers instructions that are nested within loops and are continuously otherwise fetched from the I-Cache. This mechanism is combined with code modifications, through the compiler, that greatly simplify the required hardware, eliminate unnecessary instruction fetching, and consequently reduce signal switching activity and the dissipated energy.