A multiple floating point coprocessor architecture
Lawrence Rauchwerger, P. Michael Farmwald · 1990
General purpose microprocessor based computers usu-ally speed their arithmetic processing performance by using a floating point co-processor. Because adding more co-processors represents neither a technological nor a cost problem we investigated a system based on a MIPS R2000 [2] and 4 floating point units. In this paper we show a block diagram of such an im-plementation and how two important scientific opera-tions can be accelerated using a single unmodified data bus. A large percentage of the engineering applications are solved with the help of linear algebra methods like BLAS3 [4] algorithms; It is precisely for these primi-tives that the proposed architecture brings significant performance gains. The first operation described will be a matrix multiplication algorithm, its timing dia-gram and some results. Next a polynomial evaluation technique will be examined. Finally we show how to use the same ideas with various other microprocessors. 1