Fast Placement-Intact Logic Perturbation Targeting for FPGA Performance Improvement
Catherine L. Zhou, Wai-Chung Tang, Yu‐Liang Wu · 2007
This work presents a novel, accurate, and fast post-layout logic perturbation method for improving LUT-based FPGA routing without affecting the placement. The ATPG-based rewiring techniques are used to design the rewiring engine, which is embedded into VPR, the most powerful academic FPGA CAD tool currently. Compared with VPR's high-quality results, our method can reduce critical path delay by up to 31.74% (avg. 10%) without disturbing placement or sacrificing area. The CPU time used by the rewiring engine is only 5% of the total time consumed by VPR's placement and routing. All the benchmark circuits can be placed and routed within 3 minutes, which is much faster than the SPFD approach. This paper also analyzes the power of the ATPG- based rewiring techniques in LUT-based FPGAs. Experimental results show that 3% of all nets can be replaced by their alternative wires for FPGA performance improvement.