Bit-serial multiplication in GF(2m) using irreducible all-one polynomials
S.T.J. Fenn, Michael Parker, Mohammed Benaissa, DAVID J. TAYLOR · IEE Proceedings - Computers and Digital Techniques · 1997
Two architectures for carrying out bit-serial multiplication in GF(2m) are presented where the defining irreducible polynomial for the field is an all-one polynomial. The multipliers presented have low hardware requirements, regular structures and are therefore suitable for VLSI implementation.