On the Reduction of the Number of Coefficient Circuits in a DTCNN Cell
Natalia A. Fernandez, V.M. Brea, D.L. Vilariño, D. Cabello · 2006
This paper introduces a methodology to reduce the number of coefficient circuits in a DTCNN cell without penalty at application level. Trade-offs like area-processing time, and some other figures of merit like accuracy and power dissipation are considered. It is shown that it is possible to obtain efficient implementations with a reduced number of coefficient circuits. Some examples illustrate the proposal