Constant twiddle factor multiplier sharing in multipath delay feedback parallel pipelined FFT processors
Seung‐Won Yang, Jong‐Yeol Lee · Electronics Letters · 2014
A new constant twiddle factor multiplier sharing method in parallel pipelined fast Fourier transform (FFT) processors based on a multi‐path delay feedback architecture which consists of multiple single‐path delay feedback datapaths is presented. The proposed method exploits constant twiddle factor multiplier relocation which moves a constant twiddle factor multiplier into a feedback path based on twiddle factor decomposition. By relocating a twiddle factor multiplier, the timing of twiddle factor multiplications is changed so that the multiplications with a twiddle factor are performed at different clock cycles in two datapaths, which makes it possible that the two datapaths share a multiplier operating with the twiddle factor. A reduction of 50% in the number of constant twiddle factor multipliers in the first two stages of a 128‐point four‐parallel pipelined FFT processor is achieved using the proposed method.