A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor
John D. Davis, D. Plass, Paul E. Bunce, Yiu-Hing Chan, A.R. Pelella, R. Joshi, A. Chen, William Huott, T. Knips, Pramod Kumar Patel, K. Lo, Eric J. Fluhr · 2006
A dual-read 8-way set-associative data cache comprising four 16kB SRAMs and 2 set-prediction macros per P0WER6 core is presented. The array utilizes a 0.75μm2butted-junction split-word line 6T cell in 65nm SOI. The design features dual power supplies, unidirectional polysilicon, and hierarchical undamped bit lines for enhanced cell stability and performance