Low Latency Four-Flop Synchronizer with the Handshake Interface
Suk-Jin Kim · IEICE Transactions on Information and Systems · 2005
This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.