Verification of the decimal floating-point square root operation
Amr Sayed Ahmed, Hossam A. H. Fahmy, Ulrich Kühne · 2014
Decimal floating-point is a relatively recent addition to the IEEE standard (IEEE Std 754-2008). There exist few verification techniques that can check whether software libraries or hardware designs are in compliance with the standard. Our work presents a verification method to verify implementations of the decimal floating-point square root operation. We present an effective simulation based verification technique using test cases that verify the corner cases of the operation. The test cases are generated by solving constraints describing these corner cases with a dedicated constraint solver. The generated test cases proved their usefulness by finding severe bugs in two well-tested designs.