A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architecture in 56nm
Raul Cernea, Long Duy Pham, Farookh Moogat, Siu Chan, Binh Q. Le, Yan Li, Shouchang Tsao, Tai-Yuan Tseng, Khanh Duy Tung Nguyen, Jason Li, Jayson Hu, Jong Hyuk Park, Hsu Cynthia, Zhang Fanglin, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, J. Lutze, Yingda Dong · 2008
In the diverse world of NAND flash applications, higher storage capacity is not the only imperative. Increasingly, performance is a differentiating factor and is also a way of creating new markets or expanding existing markets. While conventional memory uses, for actual operations, every other cell along a selected word line (WL) [1], this design simultaneously exercises them all. A performance improvement of at least 100% is derived from this all-bitline (ABL) architecture relative to conventional chips. Additional techniques push performance to even higher levels.