1024-point pipeline FFT processor with pointer FIFOs based on FPGA
Guanwen Zhong, Hongbin Zheng, Zhenhua Jin, Dihu Chen, Zhiyong Pang · 2011
Design and optimized implementation of a 16-bit and 32-bit 1024-point pipeline FFT processor is presented in this paper. The architecture of the FFT is based on R22SDF algorithm with new pointer FIFO embedded with gray code counters. It is implemented in Spartan-3E, Spartan-6 and Virtex-4 devices and fully tested by method of co-simulation using SMIMS®VeriLink®as a bridge that connects software(Matlab®Simulink®) and real hardware-FPGA targets. The implementation results show that our pointer FIFO FFT processor could use lower resource, but achieve higher performance. Our 16-bit 1024-point FFT processor only costs 2580 slices, 2030 slice flip flops and just 2 block RAMs, achieving the maximum clock frequency of 92.6 MHz with the throughput per area of 0.035 Msamples/s/area. Due to the parameterized input wordlength, output wordlength, Twiddle Factors wordlength and processing stages, it is easily to implement a 16-point, 64-point, 256-point, 1024-point,4096-point or higher power of 4 points pointer FIFO FFT processor synthesized from the same code just through modifying the corresponding parameters.