A decoder with OR gates for a Josephson high-density memory circuit
Takeshi Igarashi, Hideo Suzuki, S. Hasuo, Toyoshi Yamaoka · IEEE Journal of Solid-State Circuits · 1987
A decoder made of OR gates was designed for a Josephson high-density memory circuit. The advantages of this decoder are its large operating margin and high-speed operation compared with conventional decoders made of AND gates. The decoder was designed for a 16-Kbit random access memory (RAM), and was successfully operated with a delay time of 2 ns.