Accelerating reconfiguration of degradable VLSI arrays
Jigang Wu, Thambipillai Srikanthan · IEE Proceedings - Circuits Devices and Systems · 2006
The reconfiguration process within fault tolerant systems must be accelerated for the rapid generation of degradable VLSI arrays. Given an m×n mesh-connected VLSI array with faulty density ρ, finding an m′×n′ fault-free sub-array under the row and column rerouting such that m′≥r and n′≥c for integers r and c, has been shown to be NP-complete. In this paper, we propose efficient heuristic techniques based on partial rerouting strategy. We show that by enhancing popular logical row exclusion and the greedy column rerouting techniques, we reduce the routing time from O(max(m−r, n−c)·(1−ρ)·m·n) to O(β·(1−ρ)·m·n), where β≪max(m, n), without loss of harvest. Simulations based on a range of square arrays and fault densities conclusively show that the computation time can be improved by more than 70% for a fault density of 10%. Moreover, performance improvement of up to 98% is noted when the fault density is reduced to 0.1%.