FPGA based runtime configurable clause evaluatorfor SAT problems
Philip H. W. Leong, C.K. Chung · Electronics Letters · 1999
An FPGA based clause evaluator for Boolean satisfiability problems is presented in which a customised bitstream is directly generated from the problem specification, avoiding the need for resynthesis. A three orders of magnitude improvement in reconfiguration time was seen over the standard approach for a 50 variable, 80 clause problem.