Architectural improvements for data-driven VLSI processing arrays
Shlomit Weiss, I. Spillinger, Gabriel M. Siberman · 1989
In this work we explore three modifications to the architecture of a Da&-Driven VLSI array of processors, previously introduced in [I].These inodifications are geared towards improving the array utilization, as well as the performance of the mapped algorithms.The proposed modifications increase the internal paralielism present in each array processing element, improve the connecfiviry between these elements, and create blocks of processing elements to take advantage of algorithm locality.Each change is evaluated by asserting its impact on the mapping of algorithms onto the modified array.