Efficient bit-serial VLSI implementation of the 4 × 4-point discrete cosine transform
Anna Tatsaki, BOB BUREKAS, Costas E. Goutis · International Journal of Electronics · 1994
A VLSI implementation of the two-dimensional 4 × 4-point discrete cosine transform (DCTrpar; is presented. The proposed bit-serial architecture has a highly regular structure and exhibits a high data throughput rate. It is based on a high-performance application-specific multiplier. The 48-pad die size is 3922 mm2, and 13-bit accuracy DCT coefficients are produced. A performance of 188 Mpixels s−1 is achieved, which is sufficient even for the processing of high definition television signals.