Mapping Cores on Network-on-Chip
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi · International Journal of Computational Intelligence Research · 2005
The paper addresses the problem of topological mapping of intellectual properties (IPs) on the tiles of a mesh- based network on chip (NoC) architecture. The aim is to ob- tain the Pareto mappings that maximize performance and min- imize the amount of power consumption. As the problem is an NP-hard one, we propose a heuristic technique based on evolu- tionary computing to obtain an optimal approximation of the Pareto-optimal front in an efficient and accurate way. At the same time, two of the most widely-known approaches to map- ping in mesh-based NoC architectures are extended in order to explore the mapping space in a multi-criteria mode. The ap- proaches are then evaluated and compared, in terms of both accuracy and efficiency, on a platform based on an event-driven trace-based simulator which makes it possible to take account of important dynamic effects that have a great impact on mapping. The evaluation performed on real applications (an MPEG-4 codec and a cellular phone application) confirms the efficiency, accuracy and scalability of the proposed approach.