Important placement considerations for modern VLSI chips
Paul G. Villarrubia · 2003
In recent years the role of placement in the Physical Design of large chips has grown dramatically. One factor for this growth is that wire delays are increasing as a percentage of overall cycle time. As a result, placement needs to consider more than just routability of the final design. Placement is now a major contributor to timing closure results. The problem space for placement now covers a broad range of design styles, including ASIC, SOC, and Microprocessor. Each of these introduce unique challenges to placement algorithms. In addition, the ability of the placement algorithms to operate incrementally within a timing closure system is growing in significance. This talk will outline the variety of placement problems that are routinely encountered, describe major algorithmic approaches that are used to solve the problems, and discuss timing closure characteristics of different approaches.