Digital transversal filter architecture
A.J. Greenberger · Electronics Letters · 1985
A fast and efficient architecture is described for the realisation of a pipelined, fully parallel digital transversal filter in VLSI. The order of summation is changed such that no explicit multiplication is seen, gated accumulators are used, and the coefficients are circulated. Estimates for the number of transistors needed for a CMOS implementation are given.