High performance and low power modified radix-25 FFT architecture for high rate WPAN application
B Pushparaj, C Paramasivam · 2013
This paper present a high-performance and low-complexity modified radix-25512-point Fast Fourier transform (FFT) architecture using an eight data-path pipelined approach for high rate wireless personal area network applications. A novel modified radix-25FFT algorithm that reduces the hardware complexity is proposed. This method can reduce the number of complex multiplications and the size of the twiddle factor memory. It also uses a complex constant multiplier instead of a complex Booth multiplier. The results demonstrate that the total gate count of the proposed FFT architecture is 11, 894. Furthermore the highest throughput rate is up to 2.4 GS/s at 310 MHz while requiring much less hardware complexity.