Accurate layout area and delay modeling for system level design
C. N. Ramachandran, Fadi Kurdahi, Daniel D. Gajski, A.C.-H. Wu, Viraphol Chaiyakul · International Conference on Computer Aided Design · 1992
We discuss the problem of estimating design quality measures to accurately reflect design tradeofs and efficiently explore the design space. Specifreally, we are interested in predicting the layout area and delay of a given structural RT level design. Clearly, current RT level cost measures are highly simplified and do not reflect the real physical design. In order to establish a more realistic assessment of layout effects, we proposed a new layout model which accurately and efficiently accounts for the effects of wiring and Poorplanning on the area and performance layout of RT level designs. Benchmarking has shown that our model is quite accurate.