Reducing inter-vector-conflicts in complex memory systems
A. M. del Corral, José María Llabería · 1996
In vector processors, the concurrent memory access of several vector streams causes inter-conflicts between references.In a complex memory system where several memory modules are mapped in every bus the number of conflicts increases because the bus must be shared by vector streams.In addition to the memory module access conflicts, bus access conflicts can appear, and also couplings of both type of conflicts.This paper proposes an access order to the vector elements and a mapping model of memory modules in buses that reduce the inter-conflicts in the steady-state.