Instruction systolic array in image processing applications
Manfred Schimmler, Hans-Werner Lang · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1996
The ISATEC parallel computer is the first implementation of an instruction systolic array for the commercial market. The goal i\of integration of 1024 processors on an add-on-board for PCs has been achieved by the development of a low- power/low-area processor architecture whose instruction set is suited particularly for image processing applications. The paper introduces the concept of the instruction systolic array, its implementation and some application examples in the field of image processing.