An efficient design of FPGA-based sample rate converting filter in Software Defined Radio
Yuze Zhou, Chunjing Hu, Tao Peng · 2013
In order to be compatible with different sample rate requirements in communication systems, Software Defined Radio (SDR) platform must support flexible sample rate conversion. In this paper, a flexible and efficient design of FPGA-based fractional sample rate converting (SRC) filter is proposed. A folded systolic FIR structure with time-varying coefficients is introduced to lower hardware resource consumption and to relieve the timing requirement of critical path. A parameterized design methodology for high order fractional SRC filter is presented to improve the adaptability of design. A high order LTE SRC filter is implemented on a FPGA-based SDR platform for verification, and the efficiencies and the correctness are reported in the test results.