Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
Francisco Barranco, Matteo Tomasi, Javier Díaz, Mauricio Vanegas, Eduardo Ros · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2011
The proposed work presents a highly parallel architecture for motion estimation. Our system implements the well-known Lucas and Kanade algorithm with the multi-scale extension for the computation of large motion estimations in a dedicated device [field-programmable gate array (FPGA)]. Our system achieves 270 frames per second for a 640 × 480 resolution in the best case of the mono-scale implementation and 32 frames per second for the multi-scale one, fulfilling the requirements for a real-time system. We describe the system architecture, address the evaluation of the accuracy with well-known benchmark sequences (including a comparative study), and show the main hardware resources used.