Quaternary logic techniques for simplified integrated digital signal processing circuitry
K.W. Current · International Journal of Electronics · 1979
The size and complexity of some large-scale-integrated digital signal processing circuits have grown to the extent that conventional photomasking and silicon surface processing technology limitations are increasingly encountered. Intensive efforts in device minimization will eventually provide significant, increases in circuit complexity but the expense is great and development time long. An immediately viable alternative involves decoding the digital data on-chip and processing the information with quaternary or four-valued logic circuits. In this paper, a useful quaternary arithmetic circuit is described. The results of applying I his circuit in the implementation of digital parallel counters, a digital correlator and digital multipliers are then presented and compared to all binary designs. A significant saving in integrated devices is obtained in each case.