Instruction fetch energy reduction using loop caches for embedded applications with small tight loops
Lea Hwang Lee, Bill Moyer, John Arends · 1999
A fair amount of work has been done in recent years on reducing power consumption in caches by using a small instruction buffer placed between the execution pipe and a larger main cache [ 1,2,6].These techniques, however, often degrade the overall system performance.In this paper, we propose using a small instruction buffer, also called a loop cache, to save power.A loop cache has no address tag store.It consists of a direct-mapped data array and a loop cache controller.The loop cache controller knows precisely whether the next instruction request will hit in the loop cache, well ahead of time.As a result, there is no performance degradation.