A CMOS LSSD test generation system
D. Leet, P. Shearon, R. France · IBM Journal of Research and Development · 1984
Automatic test pattern generators based on the stuck-fault concept are theoretically inadequate in their ability to generate test patterns for CMOS circuits. A new set of pin faults, called CMOS faults, is discussed that can represent the necessary test pattern sequences for these circuits. Processing of these faults by a new test pattern generator, called the Enhanced Test Generator (ETG), is also described.